Tags give the ability to mark specific points in history as being important
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vfs-5.8-merge-3
e4f9ba20 · ·Third part of new DAX code for 5.8: - Teach XFS to ask the VFS to drop an inode if the administrator changes the FS_XFLAG_DAX inode flag such that the S_DAX state would change. This can result in files changing access modes without requiring an unmount cycle.
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sched-core-2020-06-02
25de110d · ·The changes in this cycle are: - Optimize the task wakeup CPU selection logic, to improve scalability and reduce wakeup latency spikes - PELT enhancements - CFS bandwidth handling fixes - Optimize the wakeup path by remove rq->wake_list and replacing it with ->ttwu_pending - Optimize IPI cross-calls by making flush_smp_call_function_queue() process sync callbacks first. - Misc fixes and enhancements. Signed-off-by: Ingo Molnar <mingo@kernel.org>
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timers-core-2020-06-02
809eb4e9 · ·The truly boring timer and clocksource updates for 5.8: - Not a single new clocksource or clockevent driver! - Device tree updates for various chips - Fixes and improvements and cleanups all over the place
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irq-core-2020-06-02
d77aeb5d · ·The generic interrupt departement provides: - Cleanup of the irq_domain API - Overhaul of the interrupt chip simulator - The usual pile of new interrupt chip drivers - Cleanups, improvements and fixes all over the place
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x86-vdso-2020-06-01
cd2f45b7 · ·Clean up various aspects of the vDSO code, no change in functionality intended. Signed-off-by: Ingo Molnar <mingo@kernel.org>
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x86_cache_updates_for_5.8
0c4d5ba1 · ·Add support for wider Memory Bandwidth Monitoring counters by querying their width from CPUID. As a prerequsite, streamline and unify the CPUID detection of the respective resource control attributes. By Reinette Chatre.
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x86-platform-2020-06-01
33649bf4 · ·This tree cleans up various aspects of the UV platform support code, it removes unnecessary functions and cleans up the rest. Signed-off-by: Ingo Molnar <mingo@kernel.org>
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x86-mm-2020-06-01
0fcfdf55 · ·Misc changes: - Unexport various PAT primitives - Unexport per-CPU tlbstate - Provide an opt-in (prctl driven) mechanism to flush the L1D cache on context switch. The goal is to allow tasks that are paranoid due to the recent snoop assisted data sampling vulnerabilites, to flush their L1D on being switched out. This protects their data from being snooped or leaked via side channels after the task has context switched out. Signed-off-by: Ingo Molnar <mingo@kernel.org>
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x86-fpu-2020-06-01
55e00fb6 · ·Most of the changes here related to 'XSAVES supervisor state' support, which is a feature that allows kernel-only data to be automatically saved/restored by the FPU context switching code. CPU features that can be supported this way are Intel PT, 'PASID' and CET features. Signed-off-by: Ingo Molnar <mingo@kernel.org>
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x86-cpu-2020-06-01
3d81b3d1 · ·Misc updates: - Extend the x86 family/model macros with a steppings dimension, because x86 life isn't complex enough and Intel uses steppings to differentiate between different CPUs. :-/ - Convert the TSC deadline timer quirks to the steppings macros. - Clean up asm mnemonics. - Fix the handling of an AMD erratum, or in other words, fix a kernel erratum. Signed-off-by: Ingo Molnar <mingo@kernel.org>
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x86-cleanups-2020-06-01
2ca41f55 · ·Misc cleanups, with an emphasis on removing obsolete/dead code. Signed-off-by: Ingo Molnar <mingo@kernel.org>
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x86-build-2020-06-01
38f3e775 · ·Misc dependency fixes, plus a documentation update about memory protection keys support. Signed-off-by: Ingo Molnar <mingo@kernel.org>