Tags give the ability to mark specific points in history as being important
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ASB-2020-08-05_4.4-o
0b832529 · ·https://source.android.com/security/bulletin/2020-08-01 CVE-2020-0255 CVE-2020-12464 CVE-2019-16746
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ASB-2020-08-05_3.18-o-mr1
aabaaab3 · ·https://source.android.com/security/bulletin/2020-08-01 CVE-2020-0255 CVE-2020-12464 CVE-2019-16746
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ASB-2020-08-05_3.18-o-release
8e1bf917 · ·https://source.android.com/security/bulletin/2020-08-01 CVE-2020-0255 CVE-2020-12464 CVE-2019-16746
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ASB-2020-08-05_3.18
8490f56c · ·https://source.android.com/security/bulletin/2020-08-01 CVE-2020-0255 CVE-2020-12464 CVE-2019-16746
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iomap-5.9-merge-5
60263d58 · ·New code for 5.9: - Make sure we call ->iomap_end with a failure code if ->iomap_begin failed in any way; some filesystems need to try to undo things. - Don't invalidate the page cache during direct reads since we already sync'd the cache with disk. - Make direct writes fall back to the page cache if the pre-write cache invalidation fails. This avoids a cache coherency problem. - Fix some idiotic virus scanner warning bs in the previous tag.
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sched-fifo-2020-08-04
4fd5750a · ·This tree adds the sched_set_fifo*() encapsulation APIs to remove static priority level knowledge from non-scheduler code. The three APIs for non-scheduler code to set SCHED_FIFO are: - sched_set_fifo() - sched_set_fifo_low() - sched_set_normal() These are two FIFO priority levels: default (high), and a 'low' priority level, plus sched_set_normal() to set the policy back to non-SCHED_FIFO. Since the changes affect a lot of non-scheduler code, we kept this in a separate tree. When merging to the latest upstream tree there's a conflict in drivers/spi/spi.c, which can be resolved via: sched_set_fifo(ctlr->kworker_task); Signed-off-by: Ingo Molnar <mingo@kernel.org>
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x86-fsgsbase-2020-08-04
d029bff6 · ·Support for FSGSBASE. Almost 5 years after the first RFC to support it, this has been brought into a shape which is maintainable and actually works. This final version was done by Sasha Levin who took it up after Intel dropped the ball. Sasha discovered that the SGX (sic!) offerings out there ship rogue kernel modules enabling FSGSBASE behind the kernels back which opens an instantanious unpriviledged root hole. The FSGSBASE instructions provide a considerable speedup of the context switch path and enable user space to write GSBASE without kernel interaction. This enablement requires careful handling of the exception entries which go through the paranoid entry path as they cannot longer rely on the assumption that user GSBASE is positive (as enforced via prctl() on non FSGSBASE enabled systemn). All other entries (syscalls, interrupts and exceptions) can still just utilize SWAPGS unconditionally when the entry comes from user space. Converting these entries to use FSGSBASE has no benefit as SWAPGS is only marginally slower than WRGSBASE and locating and retrieving the kernel GSBASE value is not a free operation either. The real benefit of RD/WRGSBASE is the avoidance of the MSR reads and writes. The changes come with appropriate selftests and have held up in field testing against the (sanitized) Graphene-SGX driver.
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x86-entry-2020-08-04
adb334d1 · ·The conversion of X86 syscall, interrupt and exception entry/exit handling to the generic code. Pretty much a straight forward 1:1 conversion plus the consolidation of the KVM handling of pending work before entering guest mode.
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timers-core-2020-08-04
31cd0e11 · ·Time, timers and related driver updates: - Prevent unnecessary timer softirq invocations by extending the tracking of the next expiring timer in the timer wheel beyond the existing NOHZ functionality. The tracking overhead at enqueue time is within the noise, but on sensitive workloads the avoidance of the soft interrupt invocation is a measurable improvement. - The obligatory new clocksource driver for Ingenic X100 OST - The usual fixes, improvements, cleanups and extensions for newer chip variants all over the driver space.
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irq-core-2020-08-04
3d5128c1 · ·The usual boring updates from the interrupt subsystem: - Infrastructure to allow building irqchip drivers as modules - Consolidation of irqchip ACPI probing - Removal of the EOI-preflow interrupt handler which was required for SPARC support and became obsolete after SPARC was converted to use sparse interrupts. - Cleanups, fixes and improvements all over the place
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core-entry-2020-08-04
3135f5b7 · ·Generic implementation of common syscall, interrupt and exception entry/exit functionality based on the recent X86 effort to ensure correctness of entry/exit vs. RCU and instrumentation. As this functionality and the required entry/exit sequences are not architecture specific, sharing them allows other architectures to benefit instead of copying the same code over and over again. This branch was kept standalone to allow others to work on it. The conversion of x86 comes in a seperate pull request which obviously is based on this branch.
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ras-core-2020-08-03
bb2de0ad · ·Boris is on vacation and he asked us to send you the pending RAS bits: - Print the PPIN field on CPUs that fill them out - Fix an MCE injection bug - Simplify a kzalloc in dev_mcelog_init_device() Signed-off-by: Ingo Molnar <mingo@kernel.org>
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x86-timers-2020-08-03
898ec52d · ·A single commit which sets the X86_FEATURE_TSC_KNOWN_FREQ flag for Xen guests, to avoid recalibration. Signed-off-by: Ingo Molnar <mingo@kernel.org>
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x86-platform-2020-08-03
3bcf25a4 · ·The biggest change is the removal of SGI UV1 support, which allowed the removal of the legacy EFI old_mmap code as well. This removes quite a bunch of old code & quirks. Signed-off-by: Ingo Molnar <mingo@kernel.org>