Tags

x86_asm_for_v5.19_rc1

- A bunch of changes towards streamlining low level asm helpers' calling
conventions so that former can be converted to C eventually

- Simplify PUSH_AND_CLEAR_REGS so that it can be used at the system call
entry paths instead of having opencoded, slightly different variants of it
everywhere

- Misc other fixes

x86_cpu_for_v5.19_rc1

- Remove a bunch of chicken bit options to turn off CPU features which
are not really needed anymore

- Misc fixes and cleanups

x86_tdx_for_v5.19_rc1

Intel Trust Domain Extensions

This is the Intel version of a confidential computing solution called
Trust Domain Extensions (TDX). This series adds support to run the
kernel as part of a TDX guest. It provides similar guest protections to
AMD's SEV-SNP like guest memory and register state encryption, memory
integrity protection and a lot more.

Design-wise, it differs from AMD's solution considerably: it uses
a software module which runs in a special CPU mode called (Secure
Arbitration Mode) SEAM. As the name suggests, this module serves as sort
of an arbiter which the confidential guest calls for services it needs
during its lifetime.

Just like AMD's SNP set, this series reworks and streamlines certain
parts of x86 arch code so that this feature can be properly accomodated.

ras_core_for_v5.19_rc1

- Simplification of the AMD MCE error severity grading logic along with
supplying critical panic MCEs with accompanying error messages for more
human-friendly diagnostics.

- Misc fixes

x86_sev_for_v5.19_rc1

AMD SEV-SNP support

Add to confidential guests the necessary memory integrity protection
against malicious hypervisor-based attacks like data replay, memory
remapping and others, thus achieving a stronger isolation from the
hypervisor.

At the core of the functionality is a new structure called a reverse
map table (RMP) with which the guest has a say in which pages get
assigned to it and gets notified when a page which it owns, gets
accessed/modified under the covers so that the guest can take an
appropriate action.

In addition, add support for the whole machinery needed to launch a SNP
guest, details of which is properly explained in each patch.

And last but not least, the series refactors and improves parts of the
previous SEV support so that the new code is accomodated properly and
not just bolted on.

x86-irq-2022-05-23

Updates for X86 PCI interrupt routing:

 - Cleanup and robustify the PCI interrupt routing table handling
   including proper range checks

 - Add support for Intel 82378ZB/82379AB, SiS85C497 PIRQ routers

 - Fix the ALi M1487 router handling

 - Handle the IRT routing table format in AMI BIOSes correctly

timers-core-2022-05-23

Updates for timers and timekeeping core code:

  - Expose CLOCK_TAI to instrumentation to aid with TSN debugging.

  - Ensure that the clockevent is stopped when there is no timer armed to
    avoid pointless wakeups.

  - Make the sched clock frequency handling and rounding consistent.

  - Provide a better debugobject hint for delayed works. The timer callback
    is always the same, which makes it difficult to identify the underlying
    work. Use the work function as a hint instead.

  - Move the timer specific sysctl code into the timer subsystem.

  - The usual set of improvements and cleanups

smp-core-2022-05-23

Updates for CPU hotplug:

  - Initialize the per CPU structures during early boot so that the state
    is consistent from the very beginning.

  - Make the virtualization hotplug state handling more robust and let the
    core bringup CPUs which timed out in an earlier attempt again.

  - Make the x86/XEN CPU state tracking consistent on a failed online
    attempt, so a consecutive bringup does not fall over the inconsistent
    state.

irq-core-2022-05-23

Updates for interrupt core and drivers:

  Core code:

    - Make the managed interrupts more robust by shutting them down in the
      core code when the assigned affinity mask does not contain online
      CPUs.

    - Make the irq simulator chip work on RT

    - A small set of cpumask and power manageent cleanups

  Drivers:

    - A set of changes which mark GPIO interrupt chips immutable to prevent
      the GPIO subsystem from modifying it under the hood. This provides
      the necessary infrastructure and converts a set of GPIO and pinctrl
      drivers over.

    - A set of changes to make the pseudo-NMI handling for GICv3 more
      robust: a missing barrier and consistent handling of the priority
      mask.

    - Another set of GICv3 improvements and fixes, but nothing outstanding

    - The usual set of improvements and cleanups all over the place

    - No new irqchip drivers and not even a new device tree binding!
      100+ interrupt chips are truly enough.

core-debugobjects-2022-05-23

Trivial licensing cleanup in debugobjects

core-core-2022-05-23

A single update for irqpoll:

  - Ensure that a raised soft interrupt is handled after pulling the
    blk_cpu_iopoll backlog from a unplugged CPU. This prevents that the CPU
    which runs that code reaches idle with soft interrupts pending.

5.4.195-402

5.4.195-403

for-5.19/block-2022-05-22

for-5.19/block-2022-05-22

for-5.19/drivers-2022-05-22

for-5.19/drivers-2022-05-22

for-5.19/cdrom-2022-05-22

for-5.19/cdrom-2022-05-22

for-5.19/writeback-2022-05-22

for-5.19/writeback-2022-05-22

for-5.19/io_uring-passthrough-2022-05-22

for-5.19/io_uring-passthrough-2022-05-22

for-5.19/io_uring-net-2022-05-22

for-5.19/io_uring-net-2022-05-22

for-5.19/io_uring-socket-2022-05-22

for-5.19/io_uring-socket-2022-05-22