Tags

locking-core-2020-10-12

These are the locking updates for v5.10:

 - Add deadlock detection for recursive read-locks. The rationale is outlined
   in:

     224ec489d3cd: ("lockdep/Documention: Recursive read lock detection reasoning")

   The main deadlock pattern we want to detect is:

           TASK A:                 TASK B:

           read_lock(X);
                                   write_lock(X);
           read_lock_2(X);

 - Add "latch sequence counters" (seqcount_latch_t):

      A sequence counter variant where the counter even/odd value is used to
      switch between two copies of protected data. This allows the read path,
      typically NMIs, to safely interrupt the write side critical section.

   We utilize this new variant for sched-clock, and to make x86 TSC handling safer.

 - Other seqlock cleanups, fixes and enhancements

 - KCSAN updates

 - LKMM updates

 - Misc updates, cleanups and fixes.

Signed-off-by: Ingo Molnar <mingo@kernel.org>

io_uring-5.10-2020-10-12

io_uring-5.10-2020-10-12

block-5.10-2020-10-12

block-5.10-2020-10-12

sched-core-2020-10-12

Scheduler changes for v5.10:

 - Reorganize & clean up the SD* flags definitions and add a bunch
   of sanity checks. These new checks caught quite a few bugs or at
   least inconsistencies, resulting in another set of patches.

 - Rseq updates, add MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ

 - Add a new tracepoint to improve CPU capacity tracking

 - Improve overloaded SMP system load-balancing behavior

 - Tweak SMT balancing

 - Energy-aware scheduling updates

 - NUMA balancing improvements

 - Deadline scheduler fixes and improvements

 - CPU isolation fixes

 - Misc cleanups, simplifications and smaller optimizations.

Signed-off-by: Ingo Molnar <mingo@kernel.org>

x86-irq-2020-10-12

Surgery of the MSI interrupt handling to prepare the support of upcoming
devices which require non-PCI based MSI handling.

  - Cleanup historical leftovers all over the place

  - Rework the code to utilize more core functionality

  - Wrap XEN PCI/MSI interrupts into an irqdomain to make irqdomain
    assignment to PCI devices possible.

  - Assign irqdomains to PCI devices at initialization time which allows
    to utilize the full functionality of hierarchical irqdomains.

  - Remove arch_.*_msi_irq() functions from X86 and utilize the irqdomain
    which is assigned to the device for interrupt management.

  - Make the arch_.*_msi_irq() support conditional on a config switch and
    let the last few users select it.

timers-core-2020-10-12

Updates for timekeeping, timers and related drivers:

 Core:

  - Early boot support for the NMI safe timekeeper by utilizing
    local_clock() up to the point where timekeeping is initialized. This
    allows printk() to store multiple timestamps in the ringbuffer which is
    useful for coordinating dmesg information across a fleet of machines.

  - Provide a multi-timestamp accessor for printk()

  - Make timer init more robust by checking for invalid timer flags.

  - Comma vs. semicolon fixes

 Drivers:

  - Support for new platforms in existing drivers (SP804 and Renesas CMT)

  - Comma vs. semicolon fixes

x86_core_for_v5.10

* Correct the "Bad RIP value" error message to be more precise, by Mark
Mossberg.

x86_asm_for_v5.10

* Use XORL instead of XORQ to avoid a REX prefix and save some bytes in
the .fixup section, by Uros Bizjak.

* Replace __force_order dummy variable with a memory clobber to fix LLVM
requiring a definition for former and to prevent memory accesses from
still being cached/reordered, by Arvind Sankar.

x86_cache_for_v5.10

* Misc cleanups to the resctrl code in preparation for the ARM side, by
James Morse.

* Add support for controlling per-thread memory bandwidth throttling
delay values on hw which supports it, by Fenghua Yu.

x86_cleanups_for_v5.10

* Misc minor cleanups.

irq-core-2020-10-12

Updates for the interrupt subsystem:

 Core:
    - Allow trimming of interrupt hierarchy to support odd hardware setups
      where only a subset of the interrupts requires the full hierarchy.

    - Allow the retrigger mechanism to follow a hierarchy to simplify
      driver code.

    - Provide a mechanism to force enable wakeup interrrupts on suspend.

    - More infrastructure to handle IPIs in the core code

 Architectures:

    - Convert ARM/ARM64 IPI handling to utilize the interrupt core code.

 Drivers:

    - The usual pile of new interrupt chips (MStar, Actions Owl, TI PRUSS,
      Designware ICTL)

    - ARM(64) IPI related conversions

    - Wakeup support for Qualcom PDC

    - Prevent hierarchy corruption in the NVIDIA Tegra driver

    - The usual small fixes, improvements and cleanups all over the place.

x86_fpu_for_v5.10

* Allow clearcpuid= to accept multiple bits, by Arvind Sankar.

* Move clearcpuid= parameter handling earlier in the boot, away from the
FPU init code and to a generic location, by Mike Hommey.

x86_fsgsbase_for_v5.10

* Misc minor cleanups and corrections to the fsgsbase code and
respective selftests.

core-debugobjects-2020-10-12

A small set of updates for debug objects:

 - Make all debug object descriptors constant. There is no reason to have
   them writeable.

 - Free the per CPU object pool after CPU unplug to avoid memory waste.

x86_misc_for_v5.10

* Ratelimit the message about writes to unrecognized MSRs so that they
don't spam the console log, by Chris Down.

* Document how the /proc/cpuinfo machinery works for future reference,
by Kyung Min Park, Ricardo Neri and Dave Hansen.

* Correct the current NMI's duration calculation, by Libing Zhou.

x86_platform_for_v5.10

* Cleanup different aspects of the UV code and start adding support for
the new UV5 class of systems, by Mike Travis.

* Use a flexible array for a dynamically sized struct uv_rtc_timer_head,
by Gustavo A. R. Silva.

x86_cpu_for_v5.10

* Add support for hardware-enforced cache coherency on AMD which
obviates the need to flush cachelines before changing the PTE encryption
bit, by Krish Sadhukhan.

* Add Centaur initialization support for families >= 7, by Tony W
Wang-oc.

* Add a feature flag for, and expose TSX suspend load tracking feature
to KVM, by Cathy Zhang.

* Emulate SLDT and STR so that windows programs don't crash on UMIP
machines, by Brendan Shanks and Ricardo Neri.

* Use the new SERIALIZE insn on Intel hardware which supports it, by
Ricardo Neri.

* Misc cleanups and fixes.

ras_updates_for_v5.10

* Extend the recovery from MCE in kernel space also to processes which
encounter an MCE in kernel space but while copying from user memory by
sending them a SIGBUS on return to user space and umapping the faulty
memory, by Tony Luck and Youquan Song.

* memcpy_mcsafe() rework by splitting the functionality into
copy_mc_to_user() and copy_mc_to_kernel(). This, as a result, enables
support for new hardware which can recover from a machine check
encountered during a fast string copy and makes that the default and
lets the older hardware which does not support that advance recovery,
opt in to use the old, fragile, slow variant, by Dan Williams.

* New AMD hw enablement, by Yazen Ghannam and Akshay Gupta.

* Do not use MSR-tracing accessors in #MC context and flag any fault
while accessing MCA architectural MSRs as an architectural violation
with the hope that such hw/fw misdesigns are caught early during the hw
eval phase and they don't make it into production.

* Misc fixes, improvements and cleanups, as always.

4.9.236-37

v5.9

Linux 5.9